1. Technical Field
The present disclosure relates to package structures, and, more particularly, to a substrate and an electronic package having the same.
2. Description of Related Art
Along with the rapid development of electronic industries, many high-end electronic products are developed toward the trend of high integration. Accordingly, various chip packaging technologies are developed and chip packaging sizes are continuously reduced to meet the miniaturization requirement of semiconductor packages.
FIG. 1 is a schematic cross-sectional view of a conventional package structure 1. The package structure 1 has a packaging substrate 10, a semiconductor chip 12 disposed on the packaging substrate 10 in a flip-chip manner, and an encapsulant 13 encapsulating the semiconductor chip 12.
Referring to FIGS. 1 and 1′, the packaging substrate 10 has a plurality of conductive pads 100, a passivation layer 101 is formed around the conductive pads 100, and an under bump metallurgy (UBM) layer 102 is formed on the conductive pads 100.
The semiconductor chip 12 is bonded to the UBM layer 102 of the conductive pads 100 through a plurality of solder bumps 11.
However, referring to FIGS. 1A and 1A′, during fabrication of the package structure 1, the packaging substrate 10 has a full-panel size (i.e., a size for mass-production), and stress concentration regions K (for example, at corners of the packaging substrate 10) are likely formed at a periphery of the semiconductor chip 12. Referring to FIG. 1A′, a region closer to the corner has more stress concentration (indicated by the density of points in FIG. 1A′) induced. Therefore, when temperature cycling or stress variation occurs in a reflow process or a drop test, the packaging substrate 10 likely warps due to a coefficient of thermal expansion (CTE) mismatch between the packaging substrate 10 and the semiconductor chip 12 (or the encapsulant 13). Consequently, solder balls 14 disposed on a lower side of the packaging substrate 10 are likely delaminated from the packaging substrate 10, and problems such as non-wetting of the solder balls 14 and cracking of the packaging substrate 10 likely occur.
Further, warpage of the packaging substrate 10 likely causes cracking of the semiconductor chip 12, and, as such, the product yield is reduced.
Therefore, how to overcome the above-described drawbacks has become critical.